This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-168760, filed Jun. 4, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device such as a field effect transistor (to be referred to as a MOSFET hereinafter) and a method of manufacturing the same and, more particularly, a semiconductor device having a silicide layer on source and drain regions and a method of manufacturing the same.
2. Description of the Related Art
In micropatterning a MOSFET serving as a main component of a semiconductor device, a so-called short channel effect, i.e., a drop of a threshold voltage along with reduction of the channel length (i.e., the length of a gate electrode layer), poses a serious problem. This short channel effect can be avoided by forming a shallow pn junction at the bottom of source and drain regions. However, if a pn junction is simply made shallow, the resistance of source and drain regions formed by the pn junction increases and impedes high-speed transmission of a signal through the device.
Recently, to decrease the resistance of a source and drain, the upper portions of source and drain regions are partially combined with a metal (silicidated). As a metal species for silicidation, an element such as Co, Ti, or Ni is used. Of these elements, only Co is free from an adverse narrow-line effect (i.e., Co shows no undesirable increase in electrical resistance when silicide is formed on a narrow silicon line) while maintaining thermal stability at high temperature (i.e., retaining compatibility with LSI manufacturing process).
However, when a silicide layer is formed on shallow source and drain regions, leakage readily occurs at the pn junction on the bottom of the source and drain regions.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
a pair of source and drain regions each formed in a surface portion of a silicon layer, and spaced from each other through a channel region in a surface portion of a silicon layer in a channel length direction;
a gate electrode layer formed on the channel region via an insulating film;
a pair of sidewall insulating films formed on sides of the gate electrode layer respectively facing the source and drain regions;
a pair of silicide layers respectively formed on the source and drain regions, and extending from the sidewall insulating films toward outer ends of the source and drain regions; and
a pair of oxygen-introduced portions respectively formed in the source and drain regions, and extending under the silicide layers from the sidewall insulating films toward the outer ends of the source and drain regions, the oxygen-introduced portions containing oxygen atoms that are locally distributed on interfaces between the silicide layers and the silicon layers of the source or drain regions at a concentration of not less than 4.5xc3x971019 cmxe2x88x923 and an areal density of not less than 5xc3x971013 cmxe2x88x922 and, and the oxygen-introduced portions forming an Ohmic contact between the silicide layers and the silicon layers of the source or drain regions.
According to a second aspect of the present invention, there is provided a method of manufacturing the semiconductor device of the first aspect, comprising:
forming the source and drain regions, using impurity ion implantation and annealing;
implanting predetermined ions to positions of the source and drain regions, which correspond to the oxygen-introduced portions, through an oxide film so as to introduce oxygen atoms in the oxide film into the source and drain regions;
depositing a metal film on the source and drain regions; and
forming the silicide layer by siliciding the metal film, using annealing.